1. Field of the Invention
The present invention relates to serial interface devices having a plurality of input bus widths, and to image forming apparatuses using such serial interface devices.
2. Description of Related Art
In image forming apparatuses such as digital still cameras, digital video cameras, or scanners, an image signal (a pixel signal) obtained by an image sensor module is typically inputted in parallel to a serial interface device provided near the image sensor module, and then undergoes predetermined image processing there. Then, only the processing result thus obtained is outputted serially to a central processing unit (hereinafter a “CPU”).
Incidentally, as the image sensor module described above, there have recently been proposed image sensor modules that use different output formats (for example, YUV output format and RAW output format) having different output bus widths. It is for this reason that highly-versatile serial interface devices that have different input bus widths so as to support any of the different output formats are sought after.
FIG. 4 is a block diagram showing an example of a conventional serial interface device. In this example, it is assumed that an 8- or 12-bit image signal DATA is inputted.
In this conventional serial interface device, the writing of the image signal DATA to a line memory block 102 is performed in such a way that the image signal DATA is written thereto eight or twelve bits at a time in parallel based on a first clock signal PCLK.
On the other hand, the reading of the image signal DATA is performed by a line memory read block 103 in such a way that, regardless of whether the stored image signal DATA is composed of eight or twelve bits, the image signal DATA is read eight bits at a time in parallel based on a second clock signal FCLK.
As a result, in a case where an 8-bit image signal DATA is stored in the line memory block 102, it is sequentially read at each pulse of the second clock signal FCLK. However, in a case where a 12-bit image signal DATA is stored, the reading thereof is performed as follows. For example, the lower eight bits (7:0) of a first image signal DATA are read at the first pulse of the second clock signal FCLK, then the upper four bits (11:8) of the first image signal DATA and the lower four bits (3:0) of a second image signal DATA are collectively read at the second pulse of the second clock signal FCLK, and then the upper eight bits (11:4) of the second image signal DATA are read at the third pulse of the second clock signal FCLK.
The second clock signal FCLK described above is a clock signal obtained by multiplying the first clock signal PCLK by a factor of 8 by a PLL (phase locked loop) circuit 106 and then dividing the frequency thereof by 8 by a frequency divider circuit 107. That is, the second clock signal FCLK is substantially the same as the first clock signal PCLK.
On the other hand, in a parallel/serial conversion block 104 (hereinafter, a “P/S block 104”), the 8-bit parallel data PDATA read by the line memory read block 103 is converted into 1-bit serial data SDATA. At this point, the P/S block 104 performs such conversion based on a third clock signal PLLCLK obtained by multiplying the first clock signal PCLK by a factor of 8.
As will be understood from the above description, this conventional serial interface device uses the line memory block 102 for temporarily storing the image signal DATA, so as to deal with an input of twelve bits while keeping the multiplication factor of the PLL circuit 106, which produces from the first clock signal PCLK the third clock signal PLLCLK needed to drive the P/S block 104, at a value (i.e., 8) appropriate for an input of eight bits.
FIG. 5 is a block diagram showing another example of a conventional serial interface device. Also in this example, it is assumed that an 8- or 12-bit image signal DATA is inputted.
This conventional serial interface device includes a first circuit group composed of: a P/S block 204a (8-bit data→1-bit data); a PLL circuit 206a (multiplication by a factor of 8); and a frequency divider circuit 207a (frequency division by 8) for dealing with an input of eight bits, and a second circuit group composed of: a P/S block 204b (12-bit data→1-bit data); a PLL circuit 206b (multiplication by a factor of 12); and a frequency divider circuit 207b (frequency division by 12) for dealing with an input of twelve bits, the first circuit group and the second circuit group being connected in parallel. With this configuration, this conventional serial interface device selectively uses one of the two circuit groups by changing a signal line built with switches 208 to 211 according to whether the inputted image signal DATA is composed of eight or twelve bits.
Some examples of another conventional technology related to what has been described thus far are seen in JP-A-2000-324285 (hereinafter “Patent Document 1”) and JP-A-H10-289032 (hereinafter “Patent Document 2”).
Certainly, with the serial interface devices shown in FIGS. 4 and 5, it is possible to convert the inputted image signal DATA into 1-bit serial data SDATA regardless of the number of bits thereof, and then transmit it to a device in the following stage.
However, the serial interface device shown in FIG. 4 has the following drawbacks. In this serial interface device, the third clock signal PLLCLK needed for parallel/serial conversion by the P/S block 104 is always produced by multiplying the first clock signal PCLK by a factor of 8, and accordingly the second clock signal FCLK needed for the reading by the line memory read block 103 has always the same frequency as that of the first clock signal PCLK.
This poses no special problem so long as the inputted image signal DATA is eight bits. However, if the inputted image signal DATA is twelve bits, since serial conversion thereof cannot be completed at each pulse of the first clock signal PCLK, it is necessary to use the line memory block 102 occupying a large layout area for storing the part of the inputted image signal DATA which is not yet converted.
Additionally, if the inputted image signal DATA is twelve bits, the serial interface device shown in FIG. 4 requires a serial output period (1.5×) 1.5 times longer than the input period (×). As a result, in a case where this serial interface device is applied to the image forming apparatus described above, as shown in FIG. 6, it is necessary to set a blanking period T (a period during which an input is prohibited) of the image signal DATA to be longer than necessary so as to prevent overlap between the output periods of the consecutive serial data SDATA. This hinders the high-speed transmission of the image signal DATA.
On the other hand, the serial interface device shown in FIG. 5 does not have the above drawbacks. However, this serial interface device requires different circuit groups (in particular, different P/S blocks operating at high speed) for dealing with an input of eight bits and an input of twelve bits separately. This leads to an unduly large device scale and an unduly high cost.
The conventional technology disclosed in Patent Document 1 simply relates to how to change the rate of transmission to the amount of information in an LVDS system having a PLL circuit on both transmission and reception sides, and is therefore completely different from the present invention.
Likewise, the conventional technology disclosed in Patent Document 2 simply relates to how to automatically check the setting of a multiplication factor by comparing the frequency of a reference clock signal with the frequency of an input clock signal, and is therefore completely different from the present invention.